1. Field
The field of the present invention relates to electronic circuit design and, in particular, to generating design constraints for electronic circuit designs.
2. Description of Related Art
Typically, a design flow at various levels of design abstraction involves specifying design constraints while different synthesis tools optimize the design around these constraints. In case of timing constraints, after synthesis, a static timing analysis is used to verify whether a design is meeting the timing budget. If this is not the case, the static timing analysis produces a critical path report. Typically, static timing analysis ignores the logic function of the gates in the design. Therefore, certain critical paths may turn out to be not sensitizable. The designer may analyze all the critical paths to determine whether a critical path is a false path or a multi-cycle path. Since false paths may not be sensitized, they should not be considered in static timing analysis. For multi-cycle paths, the timing budget may be extended to multiple clock cycles. Therefore, if such paths are found, the design constraints are modified accordingly. Otherwise, the design is modified to meet the design specification. This process continues until there are no remaining timing violations in the design.
There are many challenges in this design process. First, the design constraints are developed manually and therefore are susceptible to errors. Second, as the complexity of the designs increases, the design may be partitioned into multiple blocks. As a result, the design constraints also need to be partitioned accordingly. Maintaining correctness and consistency in the design constraints between block boundaries and between block constraints and the top-level, full-chip constraints become a challenge. For that matter, integrating block level design constraints for various IP cores developed at the block level by block owners, into top-level, full-chip design constraints for global timing analysis and synthesis, also becomes a challenge. This is a task that is usually done manually or with the aid of ad-hoc scripts. It may also be useful after the physical partitioning phase. Moreover, there might be bugs in the design which cause inconsistencies between functional behavior of a design and a design constraint specification given in a format, such as Cadence Common Timing Engine (CTE) Design Constraint Format, Synopsys Design Constraint (SDC) Format, and/or various other design constraint specifications).